Apparatuses such as electronic devices can have a clock circuit that can generate a clock signal to synchronize at least certain circuits within the electronic device. Certain electronic devices (e.g., memory devices) that employ these clock circuits can be manufactured to meet certain timing standards. Thus, a memory device that includes a clock circuit can generate a clock signal to meet a particular timing standard in order to be compatible with other electronic devices that interact with the memory device.
A signal might be generated with relatively small timing inaccuracies and/or a clock path of a circuit can introduce timing inaccuracies into the signal. These timing inaccuracies can be corrected by a duty cycle adjuster circuit (e.g., a duty cycle correction circuit) that can adjust the duty cycle of a clock signal. However, a problem with conventional duty cycle adjuster circuits is that they adjust falling edges of the clock signal to increase duty cycle, but then have to adjust rising edges of the clock signal to decrease the duty cycle. Also, when the rising edges of the clock signal are adjusted, it can impact timing and jitter performance by introducing accuracy mismatches and increasing power and lock time budgets.
FIGS. 1A and 1B illustrate typical prior art duty cycle adjuster circuits. FIG. 1A shows a schematic diagram of a circuit that can increase the duty cycle of a clock signal as shown by adjusting (e.g., skewing) the falling edges of the clock signal. A low signal on a first inverter 101 is inverted to a high signal that is inverted back to a low signal at the output of the circuit by a second inverter 102. However, the CLK OUT low signal is delayed by the gate delays resulting from the two inverters 101, 102. Thus, the resulting high signal at the node 110 between the inverters 101, 102 during that delay can enable the n-channel metal-oxide semiconductor (NMOS) transistors 103, 104 when their control gates are properly biased. A control signal on the first transistor 103 can then enable that transistor 103 and the resulting delayed high signal from the CLK OUT can enable the second transistor 104 such that the node between the two inverters is pulled down. This resulting low signal is inverted to a high signal at CLK OUT, thus adjusting the falling edges of the output clock CLK OUT.
FIG. 1B shows a circuit that can decrease the duty cycle of a clock signal as shown by adjusting the rising edges of the clock signal. The first two inverters 121, 122 provide (e.g., produce, generate, output, etc.) a substantially similar signal at the middle node 127 as the input clock CLK IN except delayed by two gate delays from the inverters 121, 122. A third inverter 123 provides an inverted clock signal that is delayed by yet another gate delay caused by the third inverter 123. These delays provide a high signal at the middle node 127 at substantially the same time that the control gates of NMOS transistors 125, 126 are biased with enable voltages from a control signal and the delayed signal from the third inverter 123. When these transistors 125, 126 turn on, they pull down the middle node 127 when normally that node would be going high, thus adjusting the rising edges of the output clock CLK OUT. However, such an adjustment of the duty cycle using the rising edges can introduce timing problems with certain standards and jitter performance problems.
There are general needs to adjust a signal duty cycle to deal with timing and jitter performance problems.